1. Technical Field
The present invention relates generally to computer systems having peripheral devices with input/output (I/O) queues, and more particularly, to techniques for estimating processor loading using peripheral transmit and receive queue depths.
2. Description of Related Art
Peripheral devices connected to a processing system typically interrupt one or more processors in order to signal the presence of receive data or absence of transmit data in device queues. In the past, an interrupt was generally generated upon receipt of a complete packet or when a complete packet had been transmitted. When an interrupt is processed, the processes triggered by the interrupt generally transfer all of the data that is available in the receive queue and likewise flush the system transmit queues by transferring transmit data to the adapter. However, when the system is experiencing a large volume of traffic, the resulting increased frequency of the interrupts received can reduce system efficiency, compounding any backlog of processing activity. Network adapters in particular have a high traffic level in today's server system and the processing overhead for handling packets can be very high, especially in a web server where the packets require a response and are not merely forwarded after minimal processing, such as in routing applications.
To solve the above-described problem, a technique known as “interrupt coalescing” has been introduced, which lessens the frequency of interrupts directed at the processor(s). Rather than interrupt at each packet transfer, present-day adapters accumulate data in queues that can accommodate multiple packets and interrupts are triggered at a lower frequency. In particular, present network adapters typically accumulate a large amount of data before interrupting the processor managing data transfer between the adapter and the host system. In part, a large data size associated with each interrupt is provided due to the overhead associated with each interrupt.
Several interrupt timing schemes have been implemented for interrupt coalescing. Three primary techniques are presently used. The first technique times a hold-off time interval from receipt of the first new packet after the last interrupt. Upon expiration of the timer, the processor is interrupted. The first technique provides adaptability only in that an interrupt will be held off for the instantaneous time between the last interrupt and completion of the first packet plus the predetermined time. If the processor is not busy, the first technique introduces undesired latency. A second technique is to interrupt after a predetermined number of packets has been received (queue depth threshold). The second technique may generate an even higher latency, as no interrupt is generated until the required number of packets is received. A third technique generates an interrupt if the frequency of packets receives drops below a predetermined threshold (received packet frequency threshold).
Each of the above-described techniques reduces interrupt overhead in the system. However, none of the techniques takes into account the processor load. Therefore, undesirable latency can be introduced when the processor is not busy and the design values such as the timer length for the first technique above, the packet count for the second technique above and the threshold value for the third technique above may not be the ideal values for high load conditions at the processor, but merely a compromise between latency and reduced interrupt overhead.
Peripheral devices other than network adapters also introduce overhead when interrupting on a per-packet basis, and therefore interrupt coalescing techniques have also been used in storage systems adapters, bus adapters such as Fiber Channel, IEEE 1394 and Universal Serial Bus (USB) adapters, with the associated problems described above.